Regviz

Cypress Semiconductor /psoc63 /FLASHC /CM0_CA_CTL0

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CM0_CA_CTL0

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Cypress Semiconductor/psoc63/FLASHC/CM0_CA_CTL0#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0WAY0SET_ADDR 0 (PREF_EN)PREF_EN 0 (ENABLED)ENABLED

Description

CM0+ cache control

Fields

WAY

Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2.
SET_ADDR

Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2.
PREF_EN

Prefetch enable: ‘0’: Disabled. ‘1’: Enabled.

Prefetching requires the cache to be enabled; i.e. ENABLED is ‘1’.
ENABLED

Cache enable: ‘0’: Disabled. The cache tag valid bits are reset to '0’s and the cache LRU information is set to '1’s (making way 0 the LRU way and way 3 the MRU way). ‘1’: Enabled.

Links

()

Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data